With a development of a semiconductor technology, a feature size of a metal-oxide-semiconductor field-effect transistor (MOSFET) is continuously scaled down. When the feature size reaches a deep submicron or even a nanometer order of magnitude, a series of degeneration effects generally appear, which do not exist or are not obvious when the feature size is a large size, such as a threshold voltage roll-off, a drain induced barrier lowering (DIBL) or an overlarge leakage current.
In order to solve above problems, one solution is that by producing a corresponding stress in a specific region of a semiconductor device according to a type thereof, a carrier mobility of the device may be enhanced, thus improving a performance of the device. In a deep submicron or nanometer device, the suitable stress is important to improve the performance of the device. Conventional methods for producing the stress comprises: adding a substitutional element in a source region and a drain region to change a lattice constant by epitaxial growth or ion implantation, depositing a stress cap layer after forming a device structure, etc. One of the most primary disadvantages of these conventional methods lies in complicated process and difficulty in adjusting stress type. Moreover, with a further scaling down of the feature size of the device, it is difficult to produce an effective stress by the conventional methods, and thus it is hard to significantly improve the performance of the semiconductor device.